Trimaran 4.0 offering:

• Support for multi-cluster architectures. The clusters can be organized as either sharing an inter-cluster communication bus or a mesh point-to-point operand network.
• Support for application-specific instruction-set extensions.
• Support for automatic vectorization .
• Support for Fortran applications via a SUIF to Trimaran translator.
• Advanced simulation of the memory system using the M5 simulator.
• Code generation infrastructure to handle ISAs with arbitrary literal bit-width constraints.
• Code generation for the ARM ISA.
• New datatype attribute associated with every operand to describe the data type (integer/float/predicate), whether the operand is signed or unsigned, and the operand bit-width.
• Support for the long long datatype.
• Register allocation has been completely rewritten and many optimizations have been added to the default path.
• Significantly improved code quality.
• Lots of bug fixes.
• A new comprehensive manual.

SUIF add-on frontend to Trimaran. This frontend implements a set of SUIF passes that convert SUIF IR to Trimaran IR (lcode). This add-on combines SUIF high level program analysis passes with the Trimaran compiler and its rich collection of machine specific optimizations. Sam Larsen's doctoral works demonstrates the value of combining frontend program analysis and backend machine optimizations in the context of automatic vectorization.

New benchmark packages are available for download.